International Conferences

 

Y. Shin, J. Kim, J. Lee, Y. Jo, and J. Choi*, "A Low-Jitter Fractional-N Sampling PLL with Voltage-Domain Quantization-Error Cancellation Using a Nonlinearity-Replication Technique," IEEE J. Solid-State Circuits (JSSC), Accepted.

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J. Kim, Y. Jo, S. Min, J. Chun, Y. Shin, H. Song, S. Kwak, K. Park*, and J. Choi*, "A 16.8–33.6Gb/s, 0.93pJ/b Direct-Frequency-Tracking Digital CDR with an SSC Profile Replicator for Per-Lane Data-Rate Variation and High Jitter Tolerance under Deep SSC," IEEE Symp. VLSI Circuits Dig., Jun. 2026.​​

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Y. Shin=, J. Lee=, J. Kim=, Y. Jo, and J. Choi*, "A 76fsrms-Jitter and −65dBc-Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024. (= Equally-Credited Authors)

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Y. Jo, J. Kim, Y. Shin, H. Park, C. Hwang, Y. Lim, and J. Choi*, "A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier," IEEE J. Solid-State Circuits (JSSC), Early Access.

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J. Kim, Y. Jo, T. Seong, H. Park, Y. Lim*, J. Choi*, "A 12.8–15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation," IEEE J. Solid-State Circuits (JSSC), Early Access.

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Y. Jo=, J. Kim=, Y. Shin, C. Hwang, H. Park, and J. Choi*, "A 135fsrms-Jitter 0.6−7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier", IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023. (= Equally-Credited Authors)

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Y. Shin=, Y. Jo=, J. Kim, J. Lee, J. Kim, and J. Choi*, "A 900μW, 1–4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces", IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023. (= Equally-Credited Authors)

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J. Kim=, Y. Jo=, Y. Lim=, T. Seong, H. Park, S. Yoo, Y. Lee, S. Choi, J. Choi*, "A 104fsRMS-Jitter and −61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation Technique," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. (= Equally-Credited Authors)

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Y. Lim=, J. Kim=, Y. Jo, J. Bang, S. Yoo, H. Park, H. Yoon and J. Choi*, "A 170MHz-Lock-In-Range and -253dB-FOMJIT, 12-14.5GHz Subsampling PLL with ...," IEEE International Solid-State Circuits Conference (ISSCC), accepted for presentation, Feb. 2020. (= Equally-Credited Authors)

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S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, and J. Choi, "153 fsRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier," IEEE Symposium on VLSI Circuits Dig., Jun. 2018, accepted for presentation

  

Journals

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Y. Shin, Y. Jo, J. Kim, J. Lee, J. Kim, and J. Choi*, "A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces," IEEE J. Solid-State Circuits (JSSC), accepted for publication.

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J. Kim, Y. Jo, T. Seong, H. Park, Y. Lim*, J. Choi*, "A 12.8–15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation," IEEE J. Solid-State Circuits (JSSC), Early Access.

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Y. Lim, J. Kim, Y. Jo, J. Bang, and J. Choi*, "A Wide-Lock-In-Range and Low-Jitter 12–14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop," IEEE Journal of Solid-State Circuits, Oct. 2021

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S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, and J. Choi*, "An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier with a Multiplication Factor of 114," IEEE Journal of Solid-State Circuits, Apr. 2018, invited from IEEE 2018 Symp. VLSI Circuits.

 

Y. Lim, J. Lee, S. Park, Y. Jo, and J. Choi*, "An External Capacitorless Low-Dropout Regulator with High PSR at All Frequencies from 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique," IEEE Journal of Solid-State Circuits, Sep. 2018

 

Awards & Honors

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25th Korea Semiconductor Design Competition, Corporate Special Award, Oct. 2024.

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30th Samsung Humantech Paper Award, Silver Award in Circuit Design, Feb. 2024.

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24th Korea Semiconductor Design Competition, Minister Award, Nov. 2023.

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2023 ISE Summer Annual Conference, Excellent Paper Award, Jul. 2023.

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2023 IDEC Congress Chip Design Contest, Excellent Design Award, Jul. 2023.

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22nd Korea Semiconductor Design Competition, Industry Special Award (Cadence Korea), Oct. 2021

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21st Korea Semiconductor Design Competition, Industry Special Award (Silicon Works), Oct. 2020

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19th Korea Semiconductor Design Competition, President of Semiconductor Association's Award, Oct. 2018

 

13th ASML Korea Semiconductor Scholarship, Oct. 2018

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Academic Activities

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Invited talk @ Samsung Semiconductor, San Jose, CA, USA, Hosted by Dr. Wanghua Wu, Feb. 2023

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Patent