​​  2024

S. Jang=, M. Chae=, H. Park, C. Hwang, and J. Choi*, "A Low-Jitter and Compact-Area Fractional-N Digital PLL with Fast Multi-Variable Calibration Using the Recursive Least Squares Algorithm," IEEE Journal of Solid-State Circuits (JSSC), Dec. 2024. (= Equally-Credited Authors)

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J. Kim=, J. Bang=, S. Jung, M. Han and J. Choi*, "A –51dBc-Reference-Spur and 66fsrms-Jitter D-Band PLL with Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector," IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2024. (= Equally-Credited Authors)

​​​​​

S. Jung, J. Kim, J. Bang, and J. Choi*, "A 45-fsrms-Jitter, 144-to-162-GHz D-Band Frequency Synthesizer Using a Subsampling PLL and a Harmonic-Boosting Frequency Multiplier," IEEE RFIC Symposium, June 2024. 

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S. Jang=, M. Chae=, H. Park=, C. Hwang, and J. Choi*, "A 5.5μs-Calibration-Time, Low-Jitter and Compact-Area Fractional-N Digital PLL Using the Recursive Least Squares (RLS) Algorithm," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024. (= Equally-Credited Authors)

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Y. Shin=, J. Lee=, J. Kim=, Y. Jo, and J. Choi*, "A 76fsrms-Jitter and −65dBc-Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024. (= Equally-Credited Authors)​

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J. Kim, Y. Jo, T. Seong, H. Park, Y. Lim*, and J. Choi*, "A 12.8–15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation," IEEE Journal of Solid-State Circuits (JSSC), Feb. 2024.

​​

  2023

Y. Jo, J. Kim, Y. Shin, H. Park, C. Hwang, Y. Lim, and J. Choi*, "A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier," IEEE Journal of Solid-State Circuits (JSSC), Dec. 2023.​

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J. Bang, S. Jung, J. Kim, S. Park, and J. Choi*, "A Sub-50-fs RMS jitter, 103.5-GHz Fundamental-Sampling PLL with an Extended Loop Bandwidth," IEEE Solid-State Circuits Letters (SSC-L), Aug. 2023.

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Y. Cho=, J. Lee=, S. Park, S. Yoo, and J. Choi, "A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102-Multiplication Factor Using a Power-Gating Technique," IEEE Symp. VLSI Circuits Dig., Jun. 2023. (= Equally-Credited Authors)

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J. Lee=, Y. Cho=, J. Kim*, and J. Choi*, "A 0.009mm2, 6.5mW, 6.2b-ENOB 2.5GS/s Flash-and-VCO-Based Subranging ADC Using a Resistor-Ladder-Based Residue Shifter," IEEE Custom Integrated Circuits Conference (CICC), Apr. 2023. (= Equally-Credited Authors)

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B. Moon, S. Lee*, and J. Choi*, "A 264−287GHz, −2.5dBm Output Power, and −92dBc/Hz 1MHz-Phase Noise CMOS Signal Source Adopting a 75fsrms Jitter D-Band Cascaded Sub-Sampling PLL," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023.

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Y. Shin=, Y. Jo=, J. Kim, J. Lee, J. Kim, and J. Choi*, "A 900μW, 1–4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023. (= Equally-Credited Authors)

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Y. Jo=, J. Kim=, Y. Shin, C. Hwang, H. Park, and J. Choi*, "A 135fsrms-Jitter 0.6−7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023. (= Equally-Credited Authors)

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J. Bang, J. Kim, S. Jung, S. Park, and J. Choi*, "A 47fsrms-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector and Extended Loop Bandwidth," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023.

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S. Park, S. Yoo, Y. Shin, J. Lee, and J. Choi*, "A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68," IEEE Journal of Solid-State Circuits (JSSC), Jan. 2023.

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  2022​

H. Park=, C. Hwang=, T. Seong, J. Choi*, "A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector," IEEE Journal of Solid-State Circuits (JSSC), Dec. 2022. (= Equally-Credited Authors)

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C. Hwang=, H. Park=, Y. Lee, T. Seong, J. Choi*, "A Low-Jitter and Low-Fractional Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC’s Second/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM," IEEE Journal of Solid-State Circuits (JSSC), Sep. 2022. (= Equally-Credited Authors)

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S. Park=, S. Choi=, S. Yoo*, Y. Cho, and J. Choi*, "An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector," IEEE Journal of Solid-State Circuits (JSSC), Sep. 2022. (= Equally-Credited Authors)

 

S. Park=, S. Yoo=, Y. Shin, J. Lee, J. Choi*, "A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked ClockMultiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2022. (= Equally-Credited Authors)

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C. Hwang=, H. Park=, T. Seong, J. Choi*, "A 188fsrms-Jitter and –243dB-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range Reduction Technique Using a Quadruple-Timing-Margin Phase Selector," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2022. (= Equally-Credited Authors)

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Y. Lim, J. Kim, Y. Jo, J. Bang, and J. Choi*, "A Wide-Lock-In-Range and Low-Jitter 12–14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop," IEEE Journal of Solid-State Circuits (JSSC), Feb. 2022.

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  2021

J. Bang, S. Choi, S. Yoo, J. Lee, J. Kim, and J. Choi*, "A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency," IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2021.

​

H. Park=, C. Hwang=, T. Seong=, Y. Lee, J. Choi*, "A 365fsRMS Jitter and −63dBc-Fractional Spur, 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC’s Second/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. (= Equally-Credited Authors)

​

S. Yoo=, S. Park=, S. Choi=, Y. Cho, H. Yoon, C. Hwang, J. Choi*, "An 82fsRMS-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector in 65nm CMOS," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. (= Equally-Credited Authors)

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J. Kim=, Y. Jo=, Y. Lim=, T. Seong, H. Park, S. Yoo, Y. Lee, S. Choi, J. Choi*, "A 104fsRMS-Jitter and −61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation Technique," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. (= Equally-Credited Authors)

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S. Yoo, S. Choi, Y. Lee, T. Seong, Y. Lim and J. Choi*, "A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator," IEEE Journal of Solid-State Circuits (JSSC), Jan. 2021.

​

  2020

​Y. Lee=, T. Seong=, J. Lee, C. Hwang, H. Park, and J. Choi*, "A -240dB-FOMJIT and -115dBc/Hz-100kHz-PN, 7.7GHz-Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020. (= Equally-Credited Authors)

​

T. Seong=, Y. Lee=, C. Hwang, J. Lee, H. Park, K. Lee, and J. Choi*, "A -58dBc-Worst Fractional Spur and -234dB-FOMJIT, 5.5GHz-Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020. (= Equally-Credited Authors)

​

Y. Lim=, J. Kim=, Y. Jo, J. Bang, S. Yoo, H. Park, H. Yoon, and J. Choi*, "A 170MHz-Lock-In-Range and -253dB-FOMJIT, 12-14.5GHz Subsampling PLL with 150μW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020. (= Equally-Credited Authors)

​​

  2019

​​

J. Lee, J. Bang, Y. Lim, S. Yoo, Y. Lee, T. Seong, and J. Choi*, "A Fast-Transient and High-Accuracy, Adaptive-Sampling Digital LDO Using a Single VCO-Based Edge-Racing Time Quantizer," IEEE Solid-State Circuits Letters (SSC-L), Oct. 2019.

​​

J. Kim, Y. Lim, H. Yoon, Y. Lee, H. Park, Y. Cho, T. Seong, and J. Choi*, "An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally-Spaced Voltage Comparators," IEEE Journal of Solid-State Circuits (JSSC), Dec. 2019.

​

S. Park, J. Kim, C. Hwang, H. Park, S. Yoo, T. Seong, and J. Choi*, "A 0.1-1.5 GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC", IEEE Microwave and Wireless Components Letters (MWCL), Aug. 2019.

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T. Seong, Y. Lee, S. Yoo, and J. Choi*, "A 320-fs RMS-Jitter and −75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC," IEEE Journal of Solid-State Circuits (JSSC), Jun. 2019.

​​

J. Lee, J. Bang, Y. Lim, and J. Choi*, "A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer," IEEE Symp. VLSI Circuits Dig., Jun. 2019.

​​

H. Yoon, S. Park, and J. Choi*, "A Low-Jitter Injection-Locked Multi-Frequency Generator using Digitally-Controlled Oscillators and Time-Interleaved Calibration," IEEE Journal of Solid-State Circuits (JSSC), Feb. 2019.

​​

S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, and J. Choi*, "An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier with a Multiplication Factor of 114," IEEE Journal of Solid-State Circuits (JSSC), Apr. 2019.

​

J. Kim=, H. Yoon=, Y. Lim=, Y. Lee, Y. Cho, T. Seong, and J. Choi*, "A 76fsRMS-Jitter and −40dBc-Integrated-Phase-Noise 28−31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019. (= Equally-Credited Authors)

​

S. Yoo, S. Choi, Y. Lee, T. Seong, Y. Lim and J. Choi*, "A 140fsRMS-Jitter and −72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019.

​

  2018

​

Y. Lim, J. Lee, S. Park, Y. Jo, and J. Choi*, "An External Capacitorless Low-Dropout Regulator with High PSR at All Frequencies from 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique," IEEE Journal of Solid-State Circuits (JSSC), Sep. 2018.

​

Y. Lim, J. Lee, Y. Lee, S. Yoo, and J. Choi*, "A 320uV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector," IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2018.

​​

K. Lim*, S. Lee, Y. Lee, Y. Lim, C. Song, J. Seong, J. Choi, and S. Han, "A 65nm CMOS 2×2 MIMO Multi-band LTE RF Transceiver for Small Cell Base Stations," IEEE Journal of Solid-State Circuits (JSSC), Jul. 2018.

​

S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, and J. Choi*, "153 fs RMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier," IEEE Symp. VLSI Circuits Dig., Jun. 2018.

​

Y. Lee, T. Seong, S. Yoo, and J. Choi*, "A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop-Filter PLL Using a Fast Phase-Error Correction Technique," IEEE Journal of Solid-State Circuits (JSSC), Apr. 2018.

​

J. Lee, S. Choi, Y. Cho, and J. Choi*, "A linearly frequency-tunable and low-phase noise ring VCO using varactors with optimally-spaced bias voltages," Electronics Letters, Mar. 2018.

​

H. Yoon, J. Kim, S. Park, Y. Lim, Y. Lee, J. Bang, K. Lim, and J. Choi*, "A -31dBc Integrated-Phase-Noise 29GHz Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward-Compatible 5G Using a Frequency Doubler and Injection-Locked Frequency Multipliers," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018.

​​

T. Seong, Y. Lee, S. Yoo, and J. Choi*, "A -242dB FOM and -75dBc-Reference-Spur Ring-DCO based All-Digital PLL Using a Fast Phase-Error Correction Technique and a Low-Power Optimal-Threshold TDC," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018.

​​

S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee, and J. Choi*, "A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier with an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers," IEEE Journal of Solid-State Circuits (JSSC), Feb. 2018. 

​​

  2017

​​

Y. Lim, J. Lee, Y. Lee, S. Song, H. Kim, O. Lee, and J. Choi*, "An External Capacitor-Less Ultra-Low Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power Supply Rejection over a Wide Range of Load Current," IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), Nov. 2017.

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S. Park, H. Yoon, and J. Choi*, "An Ultra-Low Phase Noise All-Digital Multi-Frequency Generator Using Injection-Locked DCOs and Time-Interleaved Calibration," IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2017.

​​

H. Ahn, S. Baek, I. Nam, D. Ahn, J. Lee, J. Choi, and O. Lee*, "A fully integrated dual-mode CMOS power amplifier with an autotransformer-based parallel combining transformer," IEEE Microwave and Wireless Components Letters (MWCL), Aug. 2017.

​

D. Shin, T. Seong, J. Choi*, W. Choi*, "Self-sustaining water-motion sensor platform for continuous monitoring of frequency and amplitude dynamics," Elsevier Nano Energy, May 2017. 

​

T. Seong, Y. Lee, S. Yoo, and J. Choi*, "A –242-dB FOM and –71-dBc Reference Spur Ring-VCO-based Ultra-Low-Jitter PLL," IEEE Symp. VLSI Circuits Dig., Jun. 2017.

​

Y. Lim, J. Lee, S. Park, and J. Choi*, "An External-Capacitor-less Low-Dropout Regulator with Less than –36dB PSRR at All Frequencies from 10kHz to 1GHz Using an Adaptive Supply-Ripple Cancellation Technique to the Body-Gate," IEEE Custom Integrated Circuits Conference (CICC), May 2017.

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S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee, and J. Choi*, "A PVT-Robust 29GHz Injection-Locked Frequency Multiplier with a 600uW Frequency-Tracking Loop for mm-Band 5G Transceivers," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2017.

​

  2016

​​

S. Kim, K. Kim, Y. Hwang, J. Park, Y. Kang, M. Kim, Z. Lee, J. Choi, Y. Kim, S. Jeong, B. Bae, J. Park*, "High-resolution electrohydrodynamic inkjet printing of stretchable metal oxide semiconductor transistors with high performance," Nanoscale, Sep. 2016.

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S. Choi, S. Yoo, Y. Lim, and J. Choi*, "A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier with a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector," IEEE Journal of Solid-State Circuits (JSSC), Aug. 2016.

​​

Y. Lee, H. Yoon, M. Kim, and J. Choi*, "A PVT-robust −59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop," IEEE Symp. VLSI Circuits Dig., Jun. 2016.

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H. Yoon, Y. Lee, Y. Lim, G. Tak, H. Kim, Y. Ho, and J. Choi*, "A 0.56 – 2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2 – 4G Multi-Standard Cellular Transceivers," IEEE Journal of Solid-State Circuits (JSSC), Mar. 2016.

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M. Kim, S. Choi, T. Seong, and J. Choi*, "A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-time PVT-Calibrator with Replica-Delay Cells," IEEE Journal of Solid-State Circuits (JSSC), Feb. 2016.

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S. Yoo, S. Choi, T. Seong, and J. Choi*, "An Ultra-Low Power and Compact LC-Tank-Based Frequency Tripler Using Pulsed Input Signals," IEEE Microwave and Wireless Components Letters (MWCL), Feb. 2016.

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S. Choi, S. Yoo, and J. Choi*, "A 185-fsrms Integrated-Jitter and –245-dB FOM PVT-Robust Ring-VCO-Based Injection-Locked Clock Multiplier with a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2016, Silkroad Award awarded. 

​​

  2015

​

Y. Kang, J. Choi*, and Y. Kim*, "A Wide Range On-Chip Leakage Sensor Using a Current-Frequency Converting Technique in 65-nm Technology Node," IEEE Transactions on Circuits and Systems II (TCAS-II), Sep. 2015.

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M. Kim, S. Choi, and J. Choi*, "A 450-fs Jitter PVT robust fractional-resolution injection-locked clock multiplier using a DLL-based calibrator with replica-delay-cells," in IEEE Symp. VLSI Circuits Dig., Jun. 2015.

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Y. Lee, M. Kim, T. Seong, and J. Choi*, "A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier with a Two-Phase PVT-Calibrator for ΔΣ PLLs," IEEE Transactions on Circuits and Systems I (TCAS-I), Mar. 2015.

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T. Seong, and J. Choi*, "Analysis and Design of a Core-Size-Scalable Low Phase Noise LC-VCO for Multi-Standard Cellular Transceivers," IEEE Transactions on Circuits and Systems I (TCAS-I), Mar. 2015.

​​

  2014

​​

D. Kim, S. Choi, J. Choi, and J. Kim*, "A Reconfigurable Multi-Phase LC-Ring Structure for Programmable Frequency Multiplication," IEEE Transactions on Circuits and Systems II (TCAS-II), Oct. 2014.

S. Kim, W. Eom, J. Choi, and J. Kim*, "Dual-mode wide-range linear CMOS interface circuit for resistive sensors," IET Electronics Letters, Oct. 2014.

​​

Y. Tang*, J. Choi, J. Park, L. Leung, and C. Narathong, "Varactorless tunable oscillator-patent abstracts," IEEE Journal of Solid-State Circuits (JSSC), Oct. 2014.

T. Seong, Y. Lee, and J. Choi*, "An Ultra-Low In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration," IEEE Transactions on Circuits and Systems II (TCAS-II), Sep. 2014.

​​

H. Yoon, Y. Lee, and J. Choi*, "A Wideband Dual-Mode LC-VCO With a Switchable Gate-Biased Active Core," IEEE Transactions on Circuits and Systems II (TCAS-II), Mar. 2014. 

​​

  2013

​​

S. Yoo, J. Kim, and J. Choi*, "A 2-8 GHz Wideband Dually Frequency-Tuned Ring-VCO with a Scalable Kvco", IEEE Microwave and Wireless Components Letters (MWCL), Sep. 2013.

​

Y. Tang*, J. Hu, J. Park, J. Choi*, et al., "A CMOS Highly Linear Hybrid Current/Voltage Controlled Oscillator for Wideband Polar Modulation," IEEE Transactions on Circuits and Systems I (TCAS-I), Aug. 2013.

​

  2012

 

J. Choi* et al., "A high-resolution offset-frequency PLL using properties of co-prime numbers", IET Electronics Letters, Nov. 2012.

 

Y. Tang*, J. Hu, J. Park, J. Choi, L. Leung, C. Narathong, and K. Sahoto, "A 65nm CMOS current controlled oscillator with high tuning linearity for wideband polar modulation," IEEE Custom Integrated Circuits Conference (CICC), Sept. 2012.

​

J. Choi* et al., “A Spur Suppression Technique using an Edge-Interpolator for a Charge-Pump PLL,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), May 2012.

​​

  2011

​​

S. Kim, J. Choi, K. Chae, S. Beck, S. Kim, F. Bien, C. Lee, K. Lim, J. Laskar, and M. Tentzeris, “A Non-Interruptive Link-Variation Monitoring Circuit for Wireless Sensor Applications,” IEEE Microwave and Wireless Components Letters (MWCL), Nov. 2011.

​​

J. Choi, S. Kim, et al., “A Low Power and Wide Range Programmable Clock Generator with a High Multiplication Factor,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), Apr. 2011.

 

J. Kim, K. Lee, J. Choi, et al., "Ultra-wideband CMOS voltage-controlled oscillator with reconfigurable tunable inductors," IET Electronics Letters, vol. 47, no.4. pp.249-250, Feb. 2011.

​

  2010

 

J. Kim, J. Choi, et al., "Wideband CMOS voltage-controlled oscillator using tunable inductors," IET Electronics Letters, vol.46, no.20, pp.1391-1393, Sep. 2010.

 

S. Kim, T. Song, J. Choi, et al.,“ Semi-Active High-Efficient CMOS Rectifier for Wireless Power Transmission,” IEEE RFIC Symposium, May 2010.

​

S. Kim, J. Choi, et al., “Subthreshold Current Mode Matrix Determinant Computation for Analog Signal Processing,” IEEE ISCAS, Jun. 2010.

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T. Song, J. Park, J. Choi, et al., "A 122-mW Low-Power Multiresolution Spectrum-Sensing IC With Self-Deactivated Partial Swing Techniques," IEEE Transactions on Circuits and Systems II (TCAS-II), vol.57, no.3, pp.188-192, Mar. 2010.

​​

  2009

 

J. Choi, J. Park, et al., “High Multiplication Factor Capacitor Multiplier for an On-chip PLL Loop Filter,” IET Electronics Letters, Feb. 2009.

 

J. Choi, et al., "A ring VCO with wide and linear tuning characteristics for a cognitive radio system," IEEE RFIC Symposium, pp.395-398, June 2008, nominated for the best student paper award.

​

 

  U.S. Patents

 

J. Choi, Y. Tang, “Configurable multi-mode oscillators”, WO2014008141 A1, Jan. 2014, published.

​

Y. Tang, J. Choi, C. Narathong, “Varactorless tunable oscillator”, WO2012112587 A1, Aug. 2012, published.