Yongsun Lee, Heein Yoon, Mina Kim, and Jaehyouk Choi's paper "A PVT-Robust −59-dBc Reference Spur and 450-fs RMS Jitter Injection-Locked Clock Multiplier Using a Voltage-Domain Period-Calibrating Loop" is accepted for presentation at the forthcoming Symposium on VLSI Circuits 2016 held in Honolulu, Hawaii. In this paper, voltage-domain period-calibrating loop (VDPCL) was proposed in an injection-locked clock multiplier (ILCM) to secure a low-reference-spur and low-jitter over PVT-variations. The measured spur and RMS jitter were -59 dBc and 450 fs, respectivly, and their degradations over the PVT were less than 1.5 dB and 50 fs, respectively.