Publications
J. Kim=, M. Han=, H. Song, J. Bang, Y. Lim*, and J. Choi*, "A Command-Aware Hybrid LDO with Ultra-Small Voltage Droop and Fast Settling Time for Power-Supply-Induced Jitter Mitigation in HBM Interfaces," IEEE J. Solid-State Circuits (JSSC), accepted. (= Equally-Credited Authors)

J. Kim, J. Bang, S. Jung, M. Han, and J. Choi*, "A Low-Reference-Spur and Low-Jitter D-Band PLL with Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector," IEEE Solid-State Circuits Letters (SSC-L), Aug. 2025, invited from IEEE 2024 Asian Solid-State Circuits Conference (ASSCC).

S. Jung, J. Kim, J. Bang, S. Lee, H. Yoon*, and J. Choi*, "A Low-Jitter and Wide-Frequency-Range D-Band Frequency Synthesizer with a Subsampling PLL and a Harmonic Boosting Frequency Multiplier," IEEE J. Solid-State Circuits (JSSC), May 2025, invited from IEEE 2024 RFIC Symposium. 

J. Kim=, M. Han=, J. Bang, Y. Lim and J. Choi*, "A Command-Aware Hybrid LDO for Advanced HBM Interfaces with 150μA-Quiescent Current and 20pF-On-Chip Capacitor, Achieving Sub-10mV-Voltage Droop in 400ps-Settling Time," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2025. (= Equally-Credited Authors)

J. Kim=, J. Bang=, S. Jung, M. Han and J. Choi*, "A –51dBc-Reference-Spur and 66fsrms-Jitter D-Band PLL with Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector," IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2024. (= Equally-Credited Authors)

S. Jung, J. Kim, J. Bang, and J. Choi*, "A 45-fsrms-Jitter, 144-to-162-GHz D-Band Frequency Synthesizer Using a Subsampling PLL and a Harmonic-Boosting Frequency Multiplier," IEEE RFIC Symposium, June 2024. 
 
J. Bang, S. Jung, J. Kim, S. Park, and J. Choi*, "A Sub-50-fs RMS jitter, 103.5-GHz Fundamental-Sampling PLL with an Extended Loop Bandwidth," IEEE Solid-State Circuits Letters (SSC-L), Aug. 2023, invited from IEEE 2023 International Solid-State Circuits Conference (ISSCC).

J. Bang, J. Kim, S. Jung, S. Park, and J. Choi*, "A 47fsrms-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector and Extended Loop Bandwidth," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023.


   Awards
26th Korea Semiconductor Design Competition, Corporate Special Award, Oct. 2025.

31th Samsung Humantech Paper Award, Gold Award in Circuit Design, Feb. 2025.

16th Electronic Times ICT Paper Contest, 대한전자공학회장상, Nov., 2024