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준석 프사.jpg
Junseok Lee
Dept. of Electrical and Computer Engineering, Seoul National University
Integrated Master's & Ph.D, 2024 ~ Present

   Contact Info. 
Email :
2018 - 2023
B.S. in Electrical Engineering
Korea Advanced Institute of Science and Technology

Y. Shin=, J. Lee=, J. Kim=, Y. Jo, and J. Choi*, "A 76fsrms-Jitter and −65dBc-Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024. (accepted for presentation)

Y. Shin=, Y. Jo=, J. Kim, J. Lee, J. Kim, and J. Choi*, "A 900μW, 1–4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces", IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023. (= Equally-Credited Authors)


30th Samsung Humantech Paper Award, Silver Award in Circuit Design, Feb. 2024.

24th Korea Semiconductor Design Competition, Minister Award (3rd place), 2023.11.7
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