Publications

J. Kim, Y. Jo, S. Min, J. Chun, Y. Shin, H. Song, S. Kwak, K. Park*, and J. Choi*, "A 16.8–33.6Gb/s, 0.93pJ/b Direct-Frequency-Tracking Digital CDR with an SSC Profile Replicator for Per-Lane Data-Rate Variation and High Jitter Tolerance under Deep SSC," IEEE Symp. VLSI Circuits Dig., Jun. 2026.

Y. Shin, Y. Jo, J. Kim, J. Lee, J. Kim, and J. Choi*, "A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces," IEEE J. Solid-State Circuits (JSSC), accepted for publication.

Y. Shin=, Y. Jo=, J. Kim, J. Lee, J. Kim, and J. Choi*, "A 900μW, 1–4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces", IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023. (= Equally-Credited Authors)

Awards

24th Korea Semiconductor Design Competition, Minister Award (3rd place), 2023.11.7

Patents

J. Choi, J. Kim and Y. Shin, Clock data recovery circuit used in multi-lane high-speed communication devices, Application No.: 10-2026-0025346, Feb. 9, 2026. (Domestic, Filed)