Munjae Chae
Dept. of Electrical and Computer Engineering, Seoul National University
Ph.D., 2024 ~ Present
Contact Info.
Email: munjaechae@snu.ac.kr
Email (sub): munjaechae@gmail.com
Education
2022 - 2024
M.S. in Electrical Engineering
Korea Advanced Institute of Science and Technology
2015 - 2022
B.S. in Electrical Engineering, summa cum laude
Ulsan National Institute of Science and Technology
Publications
M. Chae=, S. Jang=, S. Lee, and J. Choi*, "A Low-Jitter Fractional-N Digital PLL Using a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial-based LMS Calibration," IEEE J. Solid-State Circuits (JSSC), accepted. (= Equally-Credited Authors)
M. Chae=, S. Jang=, C. Hwang, H. Park, and J. Choi*, "A 65fsrms-Jitter and −272dB-FoMjitter,N 10.1GHz Fractional-N Digital PLL with a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial LMS Calibration," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2025. (= Equally-Credited Authors)
S. Jang=, M. Chae=, H. Park, C. Hwang, and J. Choi*, "A Low-Jitter and Compact-Area Fractional-N Digital PLL with Fast Multi-Variable Calibration Using the Recursive Least Squares Algorithm," IEEE J. Solid-State Circuits (JSSC), Dec. 2024. (= Equally-Credited Authors)
S. Jang=, M. Chae=, H. Park=, C. Hwang, and J. Choi*, "A 5.5μs-Calibration-Time, Low-Jitter and Compact-Area Fractional-N Digital PLL Using the Recursive Least Squares (RLS) Algorithm," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024.
Awards and Honors
26th Korea Semiconductor Design Competition, Corporate Special Award, Oct. 2025.
31st Samsung Humantech Paper Award, Silver Prize in Circuit Design, Feb. 2025.
25th Korea Semiconductor Design Competition, Minister Award (3rd place), Nov. 2024.
30th Samsung Humantech Paper Award, Bronze Prize in Circuit Design, Feb. 2024.